The present invention relates in general to an electrically writable non-volatile semiconductor memory device; and, more particularly, it relates to a technique that is effective for obtaining higher integration in the manufacture of non-volatile semiconductor devices.
For data storing memories having excellent portability, flash memories, which operate as semiconductor non-volatile memories, have been used generally.
A memory array system for flash memories, typically, comprise an NAND type, in which memory cells are connected in series, and an AND type, in which memory cells are connected in parallel. Particularly, since the latter type of system adopts a hot electron writing method, writing is conducted at high speed. In addition, since the memory array is constituted by a parallel connection and not a serial connection, unlike the NAND type, it has the beneficial feature of being less affected by memory information of other memory cells.
For example, Japanese Unexamined Patent Publication No. 2001-128428. (refer to Patent Document 1) discloses an imaginal grounded AND type flash memory, in which a memory cell is constituted of an n-semiconductor region (source, drain) and three gates formed in a p-type well of a semiconductor substrate.
Japanese Unexamined Patent Publication No. 2001-176275. (refer to Patent Document 2) discloses an NOR type non-volatile memory in which bit lines and source lines are respectively arranged hierarchically. The main bit line of the non-volatile memory described in the Patent Document 2. is connected as a pair of two lines (odd number bit line and even number bit line) to one sense amplifier, and reading is carried out separately for the group of memory cells connected with the odd number bit lines and those connected with the even number bit lines. Further, selection for the bit lines is conducted by a transistor (first transistor) connected to each of the odd number bit lines and the even number bit lines, and selection is controlled by a selection gate line. In one embodiment of the Patent Document 2, the first transistor comprises an enhancement transistor and a depletion transistor. According to this constitution, by arranging the normally-on depletion transistor at the intersection between the selection gate line and the auxiliary bit line, it is possible to prevent, on the intersection, formation of a parasitic transistor that turns on/off in response to a potential fluctuation of the selection gate line.    [Patent Document 1] Japanese Unexamined Patent Publication No. 2001-128428    [Patent Document 2] Japanese Unexamined Patent Publication No. 2001-176275